Markets for On-Chip and Chip-to-Chip Optical Interconnects – 2015 to 2024

Report # CIR-OI-MCC-0115
Published Jan 01, 2015

The so-called “interconnect bottleneck is creating opportunities for optical device and cable makers or all kinds. Process scaling, power consumption and operating frequency have all need to move away from metal interconnects and into the optical realm.  This need is increasing with each new node; in high performance processors with metal tracks, clock distribution alone can use up to 50% of total chip power.

In this report, CIR analyzes both the latest commercial developments in optical interconnection at the chip level (both on-chip and chip-to-chip) and the progress in this area that is being made by important research teams worldwide.  The coverage includes an investigation into the very latest architectures, devices, and materials that are impacting the prospects for on-chip and chip-to-chip optical connection.  Among the topics covered by the report are the following:

• The rise of optical engines and how these fit into future chip-to-chip connectivity.  How will the architectures of these devices and materials used change as device dimensions shrink and what is the revenue potential of optical engines over the next ten years

• An assessment of how novel photonic devices will be used in on-chip/chip-to-chip connections, analyzing the market potential of compound semiconductors versus the silicon photonics approach.

• The market for approaches to optical interconnection that uses novel materials.  Polymers, a material that has a long history, may finally find a role.  Possible roadmaps for optical interconnection that use carbon nanotubes are also considered.

• The commercialization of CMOS compatible optical interconnection using 3D architectures and other solutions

This report also contains a 10-year analysis that quantifies where and when the commercial opportunities for optical interconnection at the chip level will emerge and how much they will be worth. We also profile the leading firms and research efforts involved in designing and implementing on-chip and chip-to-chip optical interconnection.

CIR has been tracking the market for optical interconnects for almost a decade and is the leading industry analyst firm providing coverage in this this area.  The report will be of considerable interest to marketing managers, business development executives and product managers in the semiconductor and data communications industries.  It will also be of use to serious investors in these and other related industries.


Executive Summary

  • E.1 The "Interconnect Bottleneck" Spells Opportunities for the Photonics Industry
  • E.2 Interconnects at the 14-nm Node
  • E.3 Multicore Processing and Optical Interconnect
  • E.4 3D Chips and Interconnect
  • E.5 The Device Opportunity: Small and Inexpensive
  • E.5.1 The Integration Dimension: How Do You Get an Optical Link on a Chip?
  • E.5.2 An Opportunity Analysis Matrix for Chip-Level Optical Interconnection
  • E.6 Challenges for Chip-Level Optical Interconnection
  • E.6.1 Danger of Overshooting the Market
  • E.6.2 Technological Risks
  • E.7 Roadmap Considerations and Summary 10-year Forecast for Chip-Level Interconnection
  • E.8 Companies to Watch in Chip-Level Interconnection
  • E.8.1 Optical Engine Suppliers in the Chip-Level Interconnect Space
  • E.8.2 IBM, Intel and Chip-Level Interconnect
  • E.8.3 Others
  • E.9 Interconnect Implications of All-Optical Environments
Chapter One: Introduction
  • 1.1 Background to this Report
  • 1.1.1 Markets for Chip-Related Optical Interconnection: Players, Products and Opportunities
  • 1.1.2 Optical Engines and Backplanes: Immediate Revenues from Optical Interconnect?
  • 1.1.3 Emerging Technologies for Chip-Based Optical Interconnection: Long-Term Opportunities
  • 1.1.4 Closing Thoughts on the Chip-Level Interconnection Supply Chain
  • 1.2 Objectives of this Report
  • 1.3 Methodology and Information Sources for this Report
  • 1.4 Plan of this Report
Chapter Two: Analysis of Demand for On-Chip/Chip-to-Chip Interconnection
  • 2.1 Content Drivers for Optical Interconnect at the Chip Level
  • 2.1.1 The Next Data Surge: What it Means for Processors and Memories
  • 2.1.2 Interconnection's Coming Big Data Boom
  • 2.2 Optical Interconnect Megatrends
  • 2.2.1 Strategies for Dealing with the Limits of Electrical Interconnect at the Chip Level
  • 2.3 Drivers and Threats for Optical Interconnect
  • 2.4 Chip-to-Chip Interconnection
  • 2.4.1 Chip-to-Chip Optical Interconnection Considered as Market
  • 2.4.2 Emerging Supply Structure for the Chip-to-Chip Optical Interconnection Market
  • 2.5 Moore's Law and On-Chip Optical Interconnect
  • 2.5.1 The Future of Metallization and the Need for Optical Interconnect
  • 2.5.2 Alternative Materials Strategies for Future Metal Interconnect
  • 2.5.3 Current Prognosis for Moore's Law
  • 2.6 Multicore Processing and Interconnect
  • 2.6.1 Future Markets for Optical Interconnection in Multicore Processors
  • 2.6.2 Intrinsic Needs for Optical Interconnection in Multicore Processors
  • 2.7 3D Chips and Interconnect
  • 2.7.1 3D Chips and 2.5D Chips
  • 2.7.2 Opportunities for Optical Interconnection in 3D Processors
  • 2.8 A Possible Transition to Optical Computing and Communications: Interconnect Implications of All-Optical Environments
  • 2.8.1 All-Optical Backplanes
  • 2.8.2 Optical Crossconnects and Optical Switches
  • 2.8.3 Compass-EOS
  • 2.8.4 Optical Computing
  • 2.9 Threats to the Future of Chip Level Optical Interconnect
  • 2.9.1 The Interconnect Bottleneck Could be a Scare
  • 2.9.2 Intrinsic Advantages of Electrical Interconnection
  • 2.10 Key Points Made in this Chapter
Chapter Three: Technologies for On-Chip/Chip-to-Chip Interconnect
  • 3.1 Future Technologies for Chip-Level Interconnect
  • 3.2 VCSELs for Interconnect: Getting Faster
  • 3.2.1 Evolution of VCSEL Technology to Higher Data Rates
  • 3.2.2 Expected VCSEL Technology Innovations
  • 3.3 Silicon Lasers
  • 3.3.1 Intel, Lasers and Silicon Photonics
  • 3.3.2 Aurrion
  • 3.3.2 Skorpios
  • 3.4 Other Types of Lasers for Chip-Level Interconnects
  • 3.4.1 Quantum Dot Lasers
  • 3.4.2 Transistor Lasers
  • 3.4.3 Microtube Lasers
  • 3.4.4 Polariton Lasers
  • 3.4.5 Germanium-Tin Lasers
  • 3.4.6 Plasmons, Spasers and Interconnects
  • 3.5 Key Points from this Chapter
Chapter Four: Chip Level Optical Interconnection, Technology Platforms and Ten-Year Market Forecasts
  • 4.1 Optical Engines
  • 4.1.1 The Size of Optical Engines as a Problem for Chip-Level Interconnection
  • 4.1.2 Optical Engine Technology
  • 4.1.3 Optical Engine Suppliers and Products
  • 4.1.4 Ten-Year Forecast of Chip-Level Optical Interconnect Using Optical Engines
  • 4.2 The Role of Optical Integration in Future Chip-Based Interconnection
  • 4.2.1 Monolithic versus Hybrid Integration
  • 4.2.2 Integration, Interconnect and InP
  • 4.2.3 Ten-Year Forecast of Chip-Level Optical Interconnect Using PICs
  • 4.3 Silicon Photonics
  • 4.3.1 Silicon Photonics and On-Chip Photonic Interconnects
  • 4.3.2 Ten-Year Forecast of Chip-Level Optical Interconnect Using Silicon Photonics
  • 4.3.3 Fujitsu
  • 4.3.4 HP
  • 4.3.5 IBM
  • 4.3.6 IMEC/Huawei
  • 4.3.7 Intel and Omni-Scale
  • 4.3.8 NTT
  • 4.3.9 Oracle and UNIC
  • 4.3.10 Skorpios
  • 4.3.11 STMicroelectronics
  • 4.4 Opportunities for Fiber, Waveguides and Free-Space Optics in Chip-Level Interconnect
  • 4.4.1 Fiber and Interconnection
  • 4.4.2 The Role of Waveguides in Chip-Based Interconnection
  • 4.4.3 The Role of Free-Space Optics in Chip-Based Interconnection
  • 4.4.4 Ten-Year Forecast of Fiber, Wave Guides, and Free-Space Optics for Chip-Level Interconnect
  • 4.5 Use of Carbon Nanotubes and Graphene for Chip-Level Optical Interconnect
  • 4.6 Key Points Made in this Chapter
Acronyms and Abbreviations Used In this Report About the AuthorList of Exhibits
  • Exhibit E-1: Opportunity Analysis Matrix for Chip-Level Optical Interconnection
  • Exhibit 2-1: Impact of Demand Side Trends on the Need for Optical Interconnect
  • Exhibit 2-2: Selected Megatrends Impacting Optical Interconnect
  • Exhibit 2-3: Strategies for Avoiding the Interconnect Bottleneck
  • Exhibit 2-4: Advantages and Disadvantages for Optical Interconnection for Chip-Level Environments
  • Exhibit 2-5: Impact of the Emergence of Optical Computing and Communications on the Interconnect Market
  • Exhibit 3-1: Chip-Level Optical Interconnection Paradigms
  • Exhibit 3-2: Chip-Level Laser Paradigms
  • Exhibit 4-1: Selected Optical Engine Firms and Products
  • Exhibit 4-2:Ten-Year Forecasts of Chip-Level Optical Interconnect Shipments Using Optical Engines: Revenue Generation ($Millions)
  • Exhibit 4-3: Opportunities for Optical Integration in High-Speed Networks
  • Exhibit 4-4:Ten-Year Forecast of Chip-Level Optical Interconnect Shipments Using PICs: Revenue Generation ($Millions)
  • Exhibit 4-5: Ten-Year Forecast of Chip-Level Optical Interconnect Shipments Using Active Silicon Photonics: Revenue Generation ($Millions)
  • Exhibit 4-6: Chip-Level Optical Interconnection Paradigms
  • Exhibit 4-7: Ten-Year Forecast of Chip-Level Optical Interconnect Shipments Using Fiber, Waveguides and Free-Space Optics

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